1. Field of the Invention
The present invention relates to a wiring pattern of a semiconductor device, more particularly to a semiconductor device and a method of manufacturing the device in which a wiring pattern and the like are improved.
2. Description of the Related Art
In recent years, miniaturization and high integration of an inner structure of a semiconductor, and compactification of the semiconductor device have been remarkable. To meet these requirements, there have been developed a large number of various resolution enhancement technologies (RET) for forming a pattern which is fine as compared with a wavelength of a light source in, for example, a lithography process as one of processes of manufacturing the semiconductor device since the latter half of 1980s. Moreover, in this RET, for example, a transformation illumination technology has been broadly put to practical use, because a depth of focus (DOF) of a period pattern can be largely improved by comparatively simply changing an optical system. However, in recent years, reduction of the wavelength of a light source (exposure ray) or increasing of a numerical aperture (NA) of a lens cannot catch up with a request for miniaturization of a semiconductor device which has acceleratingly advanced. Specifically, it has been requested that a pattern be formed which has a pattern pitch finer than a minimum pattern pitch formable by a usual lithography technology. As one of such fine pattern forming technologies, a pattern forming technology by a so-called side-wall leaving process (side-wall transfer process) is disclosed in, for example, U.S. Pat. Nos. 5,482,885, 6,475,891 B2, 6,638,441 B2, 6,703,312 B2 and the like. There will be briefly described hereinafter the fine pattern forming method using this side-wall leaving process (not shown).
First, a resist pattern is formed on a first film composing a dummy pattern by a lithography process. Subsequently, the first film is etched using this resist pattern as a mask to form the dummy pattern. After forming the dummy pattern, the resist pattern is peeled off. Next, a second film as a material of a side wall is deposited on the dummy pattern. Thereafter, the second film is etched by, for example, a reactive ion etching (RIE) process to thereby form a foundation of a design pattern as an actual pattern on the side wall of the dummy pattern. Subsequently, after peeling the dummy pattern, a film to be worked as a substrate film is etched using the side wall as a mask. In this case, a hard mask is selected as the film to be worked, and the hard mask can be slimmed to form a finer design pattern. Moreover, when the side wall is finally peeled, the pattern formation by the side wall leaving process is ended. Accordingly, the fine design pattern is completed. It is to be noted that when the hard mask is used as the film to be worked, the hard mask is peeled after etching the film to be worked. For example, there are the following characteristics of such side-wall leaving process.
First, a pitch of the pattern formed by the lithography process may be twice a design pitch. That is, it is sufficiently possible to form a fine pattern even with an exposure device two or three generations before. The design pattern is different from a lithography target pattern (dummy pattern). The pattern can be formed into an equal pattern size on the whole surface of a substrate. The formed pattern is a closed loop pattern. Since a dimensional precision of the formed pattern is determined by an only film thickness of a side-wall material, dimension controllability is high. Furthermore, a line edge roughness of the formed pattern is small.
Among these several characteristic respects of the side-wall leaving process, the characteristic that the formed pattern becomes the closed loop pattern is a disadvantage of the side-wall leaving process. If the closed loop pattern is left as such, it is virtually impossible to complete a wiring pattern of a memory cell owing to a restriction on an inner structure, for example, in a general memory device among various semiconductor devices. Therefore, to complete the wiring pattern of the memory cell, the closed loop pattern has to be cut somewhere. That is, a step of cutting the closed loop pattern is further required. When the wiring pattern of the memory device is formed by this side-wall leaving process, the wiring pattern has to be drawn from a memory cell portion out to a peripheral circuit. However, as a result of checking by the present inventors, an effective drawing method has not been proposed yet.
Moreover, not only the wiring pattern of the memory cell formed by the side-wall leaving process but also a plurality of wiring patterns are densely formed in the same layer in the general semiconductor device. Furthermore, contact portions for electrically connecting each wiring pattern to another upper or lower wiring pattern is provided in a terminal end portion of each wiring pattern. Usually, the respective wiring patterns are cut so that the terminal end portions are linearly arranged and positioned along a direction crossing a longitudinal direction of each wiring pattern at right angles. Therefore, contact portions of the respective wiring patterns are linearly arranged along the direction crossing the longitudinal direction of each wiring pattern at right angles. However, in such structure, if misalignment is generated between each wiring and each contact plug in providing the contact plugs on the respective wirings, there is a high possibility that adjacent wirings short-circuit via the contact plugs.
To prevent such possibility beforehand, there is considered a technology to enlarge latitude (margin) of the misalignment between each wiring and each contact plug. For example, the respective contact portions are linearly arranged along a direction obliquely crossing the longitudinal direction of each wiring pattern on each wiring pattern. Accordingly, in each contact portion, it is possible to enlarge the latitude of the misalignment between each wiring and each contact plug with respect to at least the direction crossing the longitudinal direction of each wiring pattern at right angles. However, in this method, a tip portion of the wiring pattern from the contact portion becomes useless in the wiring pattern whose start end portion or intermediate portion is provided with the contact portion. Additionally, a whole tip area of each wiring pattern from the contact portion is formed as an unnecessary area for a circuit in an area of the substrate on which each wiring pattern is provided excluding an area in which a wiring pattern provided with the contact portion in its terminal end portion is formed. That is, a dead space (area penalty) of the substrate enlarges. Therefore, when the respective contact portions are simply arranged along the direction obliquely crossing the longitudinal direction of each wiring pattern, there is a remarkably high possibility that the further miniaturization, high integration, and compactification of the semiconductor device are hindered.